HIGH-SPEED PSEUDO-RANDOM BIT SEQUENCE (PRBS) PATTERN GENERATOR, ERROR DETECTOR AND ERROR COUNTER
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United States of America Patent
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Issued Date -
Jul 6, 2017
app pub date -
Dec 31, 2015
filing date -
Dec 31, 2015
priority date (Note) -
Abandoned
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Abstract
High-speed PRBS-N pattern generator, error detector and error counter circuits are provided that have relatively simple circuit configurations, that quickly synchronize and align the input data with the generated pattern, that easily and quickly detect the occurrence of a bit shifting event, and that quickly resynchronize and realign the input data with the generated pattern after a bit shifting event has occurred. The error counter may be implemented with low-speed circuitry even though the pattern generator and error detector operate at the same speed as the high-speed input data signal. This reduces the complexity and power consumption of the error counter.
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