System and method for combined path tracing in static timing analysis
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United States of America Patent
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Oct 24, 2017
Grant Date -
Jul 6, 2017
app pub date -
Jan 5, 2016
filing date -
Jan 5, 2016
priority date (Note) -
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Abstract
Aspects relate to a computer implemented method for timing analysis and pessimism removal of an integrated circuit. The computer implemented method includes performing, using a processor, a static timing analysis of the integrated circuit and generating timing data, generating a light weight path signature of a path using the generated timing data, performing common path pessimism removal (CPPR) using the light weight path signature and generating CPPR information, and storing, in a storage medium, the light weight path signature and the corresponding CPPR information. The method also includes generating a timing report using the light weight path signature and the corresponding CPPR information, wherein the timing report includes full path details generated using at least the light weight path signature, and reporting the timing report with full path details and corresponding CPPR information.
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