Extra gate device for nanosheet
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United States of America Patent
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Sep 19, 2017
Issued Date -
N/A
app pub date -
Sep 14, 2016
filing date -
Dec 30, 2015
priority date (Note) -
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Abstract
A method for forming semiconductor devices includes forming a highly doped region. A stack of alternating layers is formed on the substrate. The stack is patterned to form nanosheet structures. A dummy gate structure is formed over and between the nanosheet structures. An interlevel dielectric layer is formed. The dummy gate structures are removed. SG regions are blocked, and top sheets are removed from the nanosheet structures along the dummy gate trench. A bottommost sheet is released and forms a channel for a field effect transistor device by etching away the highly doped region under the nanosheet structure and layers in contact with the bottommost sheet. A gate structure is formed in and over the dummy gate trench wherein the bottommost sheet forms a device channel for the EG device.
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