Tunneling field-effect transistor with a plurality of nano-wires and fabrication method thereof
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United States of America Patent
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Jun 12, 2018
Issued Date -
Jul 6, 2017
app pub date -
Feb 11, 2016
filing date -
Dec 30, 2015
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Abstract
A tunneling field-effect transistor may be provided that includes: a substrate; a source which is formed on the substrate and into which p+ type impurity ion is injected; a drain which is formed on the substrate and into which n+ type impurity ion is injected; a plurality of vertically stacked nanowire channels which are formed on the substrate; a gate insulation layer which is formed on the plurality of nanowire channels; and a gate which is formed on the gate insulation layer. As a result, it is possible to generate a higher driving current without changing the length of the gate and the area of the channel (degree of integration).
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