Selective suppression of instruction translation lookaside buffer (ITLB) access
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United States of America Patent
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Feb 20, 2018
Issued Date -
N/A
app pub date -
Jan 8, 2016
filing date -
Jan 8, 2016
priority date (Note) -
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status (Latency Note)
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Abstract
Processing of an instruction fetch from an instruction cache is provided, which includes: determining whether the next instruction fetch is from a same address page as a last instruction fetch from the instruction cache; and based, at least in part, on determining that the next instruction fetch is from the same address page, suppressing for the next instruction fetch an instruction address translation table access, and comparing for an address match results of an instruction directory access for the next instruction fetch with buffered results of a most-recent, instruction address translation table access for a prior instruction fetch from the instruction cache.
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