Apparatuses and methods for accessing memory cells in semiconductor memories
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United States of America Patent
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Sep 19, 2017
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app pub date -
Jan 21, 2016
filing date -
Jan 21, 2016
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Abstract
Apparatuses and methods for accessing a memory cell are described. An example apparatus includes a first voltage circuit coupled to a node and is configured to provide a first voltage to the node and includes a second voltage circuit coupled to a node and is configured to provide a second voltage to the node. A memory cell is coupled to first and second access lines. A decoder circuit is coupled to the node and the first access line, and is configured to selectively couple the first access line to the node. The first voltage circuit is configured to provide the first voltage to the node before the second voltage circuit provides the second voltage to the node, and the second voltage circuit stops providing the second voltage before the node reaches the second voltage.
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