MULTI-CHIP SEMICONDUCTOR POWER PACKAGE
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United States of America Patent
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Issued Date -
Jul 27, 2017
app pub date -
Jan 25, 2017
filing date -
Jan 27, 2016
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Abstract
A semiconductor package is disclosed. The semiconductor package includes an electrically conducting carrier having a mounting surface, a first level first semiconductor power device having a first load electrode mounted over the mounting surface of the electrically conducting carrier and having a second load electrode opposite the first electrode. The package further includes a first level second semiconductor power device. A first connection element has a first surface connected to the second load electrode of the first level first semiconductor power device. A second connection element has a first surface connected to the second load electrode of the first level second semiconductor power device. The package includes a second level first semiconductor power device and a second level second semiconductor power device.
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