Semiconductor memory device having enlarged cell contact area and method of fabricating the same
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United States of America Patent
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Jan 2, 2018
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N/A
app pub date -
Jan 21, 2016
filing date -
Jan 21, 2016
priority date (Note) -
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Abstract
A memory array includes a semiconductor substrate having thereon a plurality of active areas and trench isolation regions between the active areas. Buried word lines are disposed in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into three portions including a digit line contact area and two cell contact areas. Buried digit lines are disposed in the semiconductor substrate above the buried word lines. An epitaxial silicon layer extends from exposed sidewalls and a top surface of each of the cell contact areas.
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