Monitoring performance of a processor using reloadable performance counters
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United States of America Patent
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Sep 19, 2017
Grant Date -
Aug 3, 2017
app pub date -
Jan 29, 2016
filing date -
Jan 29, 2016
priority date (Note) -
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Abstract
In accordance with embodiments disclosed herein, there is provided systems and methods for monitoring performance of a processor to manage events. A processor includes one or more registers to store software-visible control bits, a first performance counter to increment upon occurrence of a first type of event in the processor from a first starting value to a first limit, and a second performance counter to increment upon occurrence of a second type of event in the processor from a second starting value to a second limit. The processor also includes control logic to receive an indication of the first performance counter reaching the first limit, access a reload enable bit, and send a control signal in view of the reload enable bit. The processor also includes reload logic to reset the second performance counter to a second reload value in response to receiving the control signal from the control logic.
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