Importance

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Abstract

A method of fabricating an integrated circuit (IC) includes etching a trench in a semiconductor layer on a substrate having an aspect ratio (AR)≧5 and a trench depth≧10 μm. A dielectric liner is formed along the walls of the trench. An in-situ doped polysilicon layer having a first thickness is deposited into the trench to form a dielectric lined partially filled trench. An un-doped polysilicon layer having a second thickness greater than the first thickness is deposited on the in-situ doped polysilicon layer to complete a filling of the trench to provide a polysilicon filled trench. The doped polysilicon filler after completion of fabricating the IC is essentially polysilicon void-free and has a 25° C. sheet resistance≦60 ohms/sq. The method can include etching an opening at a bottom of the dielectric liner before depositing the polysilicon to provide ohmic contact to the semiconductor layer.

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First Claim