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Abstract

A multi-state phase shifter circuit having both low insertion loss (IL) and good return loss. Two or more phase shift elements are combined into a single cell architecture to reduce the number of series-connected FET switches and reduce the total IL. One embodiment has two ports connected by parallel signal paths each comprising a pair of switches and a phase shift element comprising, for example, an inductor, a capacitor, a transmission line, or a conductor. Another embodiment has two ports connected by parallel signal paths each comprising a switch and at least one associated phase shift element. The switches in each parallel signal path allow the associated phase shift element to be placed in-circuit under the control of an applied signal. The sets of switches may be independently controlled, so that multiple parallel signal paths may be switched into circuit between the phase shifter circuit ports at the same time.

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First Claim