System aware transmitter adaptation for high speed serial interfaces
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United States of America Patent
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Mar 20, 2018
Issued Date -
N/A
app pub date -
Apr 26, 2017
filing date -
Nov 7, 2014
priority date (Note) -
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Abstract
A high-speed serial interface includes a transmitter having an output module with settings that select an output impedances of the output module and a tuning value for the output impedance, and a receiver having a plurality of compensation modules each to provide a selectable level of equalization to a data bitstream from the transmitter, and a control module that directs the transmitter to successively select each of the tuning values, that directs the compensation modules, for each tuning value, to successively select each of the levels of equalization, that evaluates an indication of a performance level of the receiver for each of the successively selected levels of equalization and for each of the tuning values, and that selects a particular tuning value based upon the indications of the performance level of the receiver.
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