Importance

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Abstract

According to various embodiments, a transistor model for a computer based simulation of a field effect transistor may include: a first electrical network coupled between a drain node, a source node and a gate node, wherein the first electrical network is configured to represent an electrical characteristic of the field effect transistor in a forward operation; a second electrical network coupled parallel to the first electrical network and between the source node and the drain node, wherein the second electrical network is configured to represent an electrical characteristic of the field effect transistor in at least one of a commutation operation and a reverse operation; wherein the second electrical network includes: a controlled first source representing a parasitic junction of the field effect transistor; at least one controlled second source representing a charge injection dependent parasitic impedance of the field effect transistor; wherein the controlled first source and the at least one controlled second source are coupled in parallel; and wherein the controlled first source and the at least one controlled second source are coupled via at least one parameter such that a charge injection from the parasitic junction into the parasitic impedance is considered.

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First Claim