Implementing a received add program counter immediate shift (ADDPCIS) instruction using a micro-coded or cracked sequence
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United States of America Patent
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Mar 19, 2019
Grant Date -
Aug 31, 2017
app pub date -
Jun 10, 2016
filing date -
Feb 25, 2016
priority date (Note) -
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Abstract
A computer program product for implementing a received add program counter immediate shift (ADDPCIS) instruction using a micro-coded or cracked sequence is provided. The computer program product includes a computer readable storage medium having program instructions embodied therewith. The program instructions are readable and executable by a processing circuit to cause the processing circuit to recognize register operand and integer terms associated with the ADDPCIS instruction, set a value of a target register associated with the ADDPCIS instruction in accordance with the integer term summed with another term by obtaining a next instruction address (NIA), moving an architecturally defined register file from a first temporary register to a general purpose register and adding a shifted immediate constant to a value stored in a second temporary register.
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