DRAM controller with adaptive precharge policy
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United States of America Patent
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Nov 20, 2018
Grant Date -
Sep 7, 2017
app pub date -
Feb 28, 2017
filing date -
Mar 1, 2016
priority date (Note) -
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Abstract
A Dynamic Random Access Memory (DRAM) controller includes a memory interface and a processor. The memory interface is configured to communicate with a DRAM including one or more memory banks. The processor is configured to receive Input/Output (I/O) commands, each I/O command addressing a respective memory bank and a respective row within the memory bank to be accessed in the DRAM, to further receive one or more indications, indicative of likelihoods that a subsequent I/O command will address a same row in a same memory bank as a previous I/O command, to adaptively set, based on the indications, a policy of deactivating rows of the DRAM, and to execute the I/O commands in the DRAM in accordance with the policy.
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