Bypassing an encoded latch on a chip during a test-pattern scan
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United States of America Patent
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Mar 6, 2018
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app pub date -
Mar 8, 2016
filing date -
Mar 8, 2016
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Abstract
Aspects include techniques for bypassing an encoded latch on a chip during a test-pattern scan and using on-chip circuitry to generate a desired encoded pattern, which is inserted into a scan-bypassed latch, to test the on-chip circuitry for defects. A computer-implemented method may include applying a global control bit to the chip; initializing a scan of the chip while bypassing the encoded latch; and applying an extra scan clock to initiate the encoded latch after completing the scan, wherein the encoded latch is updated with check bits generated by the on-chip circuitry.
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