Code partitioning for the array of devices

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United States of America Patent

PATENT NO 10326448
APP PUB NO 20170262567A1
SERIAL NO

15608764

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Abstract

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According to an aspect of an embodiment, a method of array source code partitioning and topology determination may include determining an optimum topology of an array of field programmable gate array (FPGA) devices based on a processing specification. The method may include automatically performing the best-effort partitioning on a default topology of the array of FPGA devices. The method may include partitioning parallel and serial source code among the FPGA devices mapped into optimum topology or the default topology. The method may include mapping a virtual topology onto a fixed physical topology of the array of FPGA devices. The method may include presenting computing resources of the array of FPGA devices to a host or to an entire application as a larger FPGA or as software-defined computing resources.

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Patent Owner(s)

  • SCIENTIFIC CONCEPTS INTERNATIONAL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Vassiliev, Andrei V Plano, US 3 85

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