Instruction, Circuits, and Logic for Data Capture for Software Monitoring and Debugging
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United States of America Patent
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Issued Date -
Oct 5, 2017
app pub date -
Apr 1, 2016
filing date -
Apr 1, 2016
priority date (Note) -
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Abstract
A processor includes a front end including circuitry to receive an instruction to monitor execution of a thread, a decoder including circuitry to decode the instruction, a scheduler including circuitry to schedule the instruction, a retirement unit including circuitry to retire the instruction, and a core. The core includes circuitry to, based on execution of the instruction, monitor execution of the thread, identify an attempted read of an address during execution of the thread, determine whether a value at the address was previously read during monitoring of the execution of the thread, log the attempted read based on a determination that the value at the address was not previously read during monitoring of the execution of the thread, and omit logging of the attempted read based on a determination that the value at the address was previously read during monitoring of the execution of the thread.
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