Processors, methods, systems, and instructions to atomically store to memory data wider than a natively supported data width
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United States of America Patent
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Jan 26, 2021
Grant Date -
Oct 5, 2017
app pub date -
Apr 2, 2016
filing date -
Apr 2, 2016
priority date (Note) -
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status (Latency Note)
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Abstract
A processor includes a widest set of data registers that corresponds to a given logical processor. Each of the data registers of the widest set have a first width in bits. A decode unit that corresponds to the given logical processor is to decode instructions that specify the data registers of the widest set, and is to decode an atomic store to memory instruction. The atomic store to memory instruction is to indicate data that is to have a second width in bits that is wider than the first width in bits. The atomic store to memory instruction is to indicate memory address information associated with a memory location. An execution unit is coupled with the decode unit. The execution unit, in response to the atomic store to memory instruction, is to atomically store the indicated data to the memory location.
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