Handling of error prone cache line slots of memory side cache of multi-level system memory
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United States of America Patent
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Jan 22, 2019
Grant Date -
Oct 5, 2017
app pub date -
Mar 31, 2016
filing date -
Mar 31, 2016
priority date (Note) -
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Abstract
An apparatus is described that includes memory controller logic circuitry to interface with a memory side cache of a multi-level system memory. The memory controller logic circuitry includes error tracking circuitry to track errors of cache line slots in the memory side cache. The memory controller logic circuitry also comprises faulty list circuitry to store identifiers of faulty cache line slots that are deemed to be excessively error prone. The memory controller logic circuitry is to declare a miss in the memory side cache for requests that map to cache line slots identified in the faulty list.
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