ENERGY EFFICIENT READ/WRITE SUPPORT FOR A PROTECTED MEMORY
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United States of America Patent
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Issued Date -
Oct 5, 2017
app pub date -
Apr 1, 2016
filing date -
Apr 1, 2016
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status (Latency Note)
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Abstract
Technology for an apparatus is described. The apparatus can include a memory controller with circuitry configured to read K bits of M bits of encoded data in memory, D error detection bits, and P Parity bits protecting the M bits of encoded data for performing a read-write-modify (RWM) command operation on the K bits of the M bits encoded data, wherein K, M and D are positive integers and P is a vector of a set of parity bits. The memory controller can determine whether an error is present on the K bits of the M bits of encoded data according to the D error detection bits.
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