Importance

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Abstract

A system includes a repeater architecture for commands where memory connects to a host for with one bandwidth, and repeats the channel with a lower bandwidth. A memory circuit includes a first group of command signal lines to couple point-to-point between a first group of memory devices and a host device. The memory circuit includes a second, smaller group of command signal lines to couple point-to-point between the first group of memory devices and a second group of memory devices, to extend the memory channel to the second group of memory devices. The memory circuit includes a repeater to share the command bandwidth between the first and second groups of memory devices, with up to a portion of the bandwidth for commands to the second group of memory devices, and at least an amount equal to the bandwidth less the portion for commands to the first group of memory devices.

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First Claim