ARITHMETIC PROCESSING DEVICE, METHOD, AND SYSTEM

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United States of America Patent

APP PUB NO 20170300322A1
SERIAL NO

15478528

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Abstract

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An arithmetic processing device includes: an instruction control circuit; primary cache circuit that includes a primary cache memory and a first buffer; and a secondary cache memory. The primary cache circuit is configured to, when a first instruction for executing processing to register data of a cache line in the secondary cache memory without the occurrence of an access to the main memory, is issued from the instruction control circuit and when data corresponding to a first address designated as an access target in the first instruction is not stored in the primary cache memory, store the first address in the first buffer and issue the first instruction to the secondary cache memory.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
FUJITSU LIMITEDKAWASAKI18047

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