Importance

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Abstract

The invention concerns a system on a chip (100) comprising a set of master modules which includes a main processing module (101a) and a direct memory access controller (DMA) (102a) associated with said module (101a), and at least one secondary processing module (101b) and a DMA (102b) associated with said module (101b), and slave modules; each master module being configured for connection to a clock source, a power supply, and slave modules which include a set of proximity peripherals (105a,b), at least one internal memory (104a,b) and a set (106) of peripherals and external memories shared by the master modules; said clock source, power supply, proximity peripherals (105a,b) and a cache memory (103a,b) of a master processing module and its DMA being dedicated to said master processing module and not shared with the other processing modules of the set of master modules; and said at least one internal memory (104a,b) of each master processing module and its DMA being dedicated to said master processing module, said main processing module (101a) being nevertheless able to access same.

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First Claim