COMPUTER SECURITY FRAMEWORK AND HARDWARE LEVEL COMPUTER SECURITY IN AN OPERATING SYSTEM FRIENDLY MICROPROCESSOR ARCHITECTURE

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United States of America Patent

SERIAL NO

15474263

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Abstract

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A microprocessor computer system for secure/high assurance/safety critical computing includes a hardware subsystem having a plurality of cache controller and cache bank modules including cache bank and memory cell hardware permission bits for managing and controlling access to system resources. A computer security framework subsystem includes a hierarchy of access layers comprising top layers and lower layers. The permission bits provide hardware level computer security primitives for a computer operating system. The top layers are completely trusted and the lower layers are moderately trusted to completely untrusted. The top layers include a trusted operating system layer that executes management and control of the system resources and permission bits. The permission bits define limits for a hardware execution security mechanism for less trusted to completely untrusted software. Exceeding bounds of the security mechanism results in a hardware exception thereby blocking all attempts to access or modify resources outside the security mechanism.

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Patent Owner(s)

Patent OwnerAddress
ARMY UNITED STATES OF AMERICA AS REPRESENTED BY THE SECRETARY OF THEU S ARMY CORPS OF ENGINEERS HUMPHREY ENGINEER CENTER CEHEC-OC (KINGMAN BUILDING) 7701 TELEGRAPH ROAD ALEXANDRIA VA 22315

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
JUNGWIRTH, PATRICK W Abingdon, US 6 64

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