Memory and memory control method

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United States of America Patent

PATENT NO 10002670
SERIAL NO

15465700

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Abstract

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A memory includes a memory cell including a memory transistor in which electric charges are stored in an electric charge storage layer when data is written to the memory cell, and a controller configured to control a voltage to be applied to the memory transistor in a predetermined hold time until an amount of electric charges stored in the electric charge storage layer decreases to an amount of electric charges corresponding to a state where the data is erased from the memory cell.

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Patent Owner(s)

  • FUJITSU LIMITED

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ise, Masahiro Machida, JP 36 432
Maeda, Masazumi Yokohama, JP 10 9

Cited Art Landscape

Patent Info (Count) # Cites Year
 
TOSHIBA MEMORY CORPORATION (1)
* 2007/0030,747 Data recording device 3 2006
 
SANDISK TECHNOLOGIES LLC (1)
* 2010/0238,729 NON-VOLATILE MEMORY WITH REDUCED LEAKAGE CURRENT FOR UNSELECTED BLOCKS AND METHOD FOR OPERATING SAME 16 2009
 
SEAGATE TECHNOLOGY LLC (1)
* 2010/0302,849 NAND FLASH MEMORY WITH INTEGRATED BIT LINE CAPACITANCE 3 2009
 
MICRON TECHNOLOGY, INC. (1)
* 2004/0004,245 Memory utilizing oxide-conductor nanolaminates 14 2002
 
ADESTO TECHNOLOGY CORPORATION (1)
* 2014/0003,125 Resistive Devices and Methods of Operation Thereof 7 2012
 
NXP USA, INC. (1)
* 2009/0097,323 BITLINE CURRENT GENERATOR FOR A NON-VOLATILE MEMORY ARRAY AND A NON-VOLATILE MEMORY ARRAY 5 2006
 
INFINEON TECHNOLOGIES AG (1)
* 2011/0103,150 NON-VOLATILE MEMORY WITH PREDICTIVE PROGRAMMING 9 2009
* Cited By Examiner

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