Operation of a multi-slice processor implementing exception handling in a nested translation environment
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United States of America Patent
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Aug 7, 2018
Grant Date -
Oct 26, 2017
app pub date -
Apr 26, 2016
filing date -
Apr 26, 2016
priority date (Note) -
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Abstract
Operation of a multi-slice processor that includes a plurality of execution slices, a plurality of load/store slices, and one or more translation caches, where operation includes: determining, at the load/store slice, a real address from a cache hit in the translation cache for an effective address for an instruction received at a load/store slice; determining, at the load/store slice, an error condition corresponding to an access of the real address; determining, at the load/store slice, a process type indicating a source of the instruction to be a guest process; and responsive to determining the error condition, initiating, in dependence upon the process type indicating a source of the instruction to be a guest process, an effective address translation corresponding to a cache miss in the translation cache for the effective address for the instruction.
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