TERMINAL APPARATUS AND FAILURE RESPONSE CONTROL METHOD
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United States of America Patent
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Mar 25, 2017
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Apr 26, 2016
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Abstract
A terminal apparatus includes a memory that has a program area divided in a plurality of blocks, each blocks being set write protection, and a processor coupled to the memory and configured to set a priority level of stored data to each blocks of the memory, respectively, change the priority level to a lower level in accordance with a failure of an internal of the terminal apparatus when the failure is detected, release the write protection in accordance with the changed priority level, and write data that has a possibility of elimination, to the block whose write protection has released, in accordance with the failure.
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