Continuous write and read operations for memories with latencies
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United States of America Patent
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May 15, 2018
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app pub date -
Apr 25, 2016
filing date -
Apr 25, 2016
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Abstract
A method and apparatus for continuous write and read operations during memory testing. The method comprises: controlling a signal generator; triggering a write address and a data field operation each memory cycle; triggering a write signal to write to a memory each memory clock cycle; and reading a read address and a read data operation to the memory. An additional embodiment provides an apparatus for advanced memory latency testing. The apparatus includes a data generator trigger in communication with a signal generator and an address generator trigger also in communication with the signal generator.
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