Structures and Methods for Reliable Packages

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United States of America Patent

SERIAL NO

15649457

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Abstract

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A device and method of forming the device that includes cavities formed in a substrate of a substrate device, the substrate device also including conductive vias formed in the substrate. Chip devices, wafers, and other substrate devices can be mounted to the substrate device. Encapsulation layers and materials may be formed over the substrate device in order to fill the cavities.

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Patent Owner(s)

Patent OwnerAddress
ADEIA SEMICONDUCTOR TECHNOLOGIES LLC3025 ORCHARD PARKWAY SAN JOSE CA 95134

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Gao, Guilian San Jose, US 126 2767
Shen, Hong Palo Alto, US 238 3099
Sitaram, Arkalgud R Cupertino, US 63 1400
Uzoh, Cyprian Emeka San Jose, US 330 9133
Wang, Liang Milpitas, US 570 4781

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