Memory system with independently adjustable core and interface data rates

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United States of America Patent

PATENT NO 10671561
APP PUB NO 20170315953A1
SERIAL NO

15626038

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Abstract

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An integrated circuit device is disclosed including core circuitry and interface circuitry. The core circuitry outputs in parallel a set of data bits, while the interface circuitry couples to the core circuitry. The interface circuitry receives in parallel a first number of data bits among the set of data bits from the core circuitry and outputs in parallel a second number of data bits. The ratio of the first number to the second number is a non-power-of-2 value.

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Patent Owner(s)

Patent OwnerAddress
RAMBUS INC1050 ENTERPRISE WAY SUITE 700 SUNNYVALE CA 94089

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ware, Frederick A Los Altos Hills, US 760 10960

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