Integrated interposer solutions for 2D and 3D IC packaging
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United States of America Patent
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Apr 9, 2019
Grant Date -
Nov 2, 2017
app pub date -
Jul 17, 2017
filing date -
Jun 4, 2014
priority date (Note) -
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status (Latency Note)
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Abstract
An integrated circuit (IC) package includes a first substrate having a backside surface and a top surface with a cavity disposed therein. The cavity has a floor defining a front side surface. A plurality of first electroconductive contacts are disposed on the front side surface, and a plurality of second electroconductive contacts are disposed on the back side surface. A plurality of first electroconductive elements penetrate through the first substrate and couple selected ones of the first and second electroconductive contacts to each other. A first die containing an IC is electroconductively coupled to corresponding ones of the first electroconductive contacts. A second substrate has a bottom surface that is sealingly attached to the top surface of the first substrate, and a dielectric material is disposed in the cavity so as to encapsulate the first die.
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