Synchronous input/output computer system including hardware invalidation of synchronous input/output context
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United States of America Patent
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Jul 30, 2019
Grant Date -
Nov 9, 2017
app pub date -
May 9, 2016
filing date -
May 9, 2016
priority date (Note) -
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Abstract
A synchronous input/output (I/O) computing system includes a processor and a memory unit that stores program instructions. The system is configured to purge a device table cache (DTC) in response to the processor executing the program instructions. An operating system runs on the synchronous I/O computing system and issues a synchronous I/O command indicating a request to perform a device table entry transaction that has a total data length to be transferred. A device table entry is selected from a device table, loaded into the DTC, and data packets corresponding to the device table entry transaction are transferred using the selected device table entry. A host bridge processor monitors the data packets transferred using the selected table entry, and automatically purges the selected device table entry from the DTC in response to determining the transferred data packets match the total data length.
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