3D semiconductor memory device and manufacturing method thereof
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United States of America Patent
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Jan 2, 2018
Issued Date -
N/A
app pub date -
Sep 28, 2016
filing date -
May 4, 2016
priority date (Note) -
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Abstract
Provided herein is a semiconductor device including: a channel layer; a data storage layer surrounding the channel layer and extending along the channel layer; interlayer insulating layers surrounding the data storage layer and stacked along the channel layer, wherein the interlayer insulating layers are spaced apart from each other, wherein a conductive area is disposed between the interlayer insulating layers; a conductive pattern disposed in the conductive area and surrounding the data storage layer; buffer patterns disposed between the interlayer insulating layers and the data storage layer and surrounding the data storage layer, wherein each of the buffer patterns includes a densified area, wherein the buffer patterns are separated from each other by the conductive area; and a blocking insulating pattern disposed between the conductive pattern and the data storage layer and surrounding the data storage layer.
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