EMBEDDED PARITY MATRIX GENERATOR
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United States of America Patent
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May 6, 2016
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May 6, 2016
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Abstract
A circuit, including an embedded parity matrix generator configured to generate a parity matrix for a data word of any data width; an encoder configured to add a redundancy word to the data word based on the parity matrix; a sub-circuit coupled to the encoder, and configured to receive the data word and the redundancy word from the encoder; and a decoder coupled to the sub-circuit, and configured to receive the data word and the redundancy word from the sub-circuit, and to detect any errors in the data word based on the parity matrix.
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