Wide-range clock signal generation for speed grading of logic cores

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 10317462
APP PUB NO 20170328952A1
SERIAL NO

15592763

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

An integrated circuit for on-chip speed grading comprises test circuitry comprising scan chains and a test controller; and wide-range clock signal generation circuitry comprising phase-locked loop circuitry and frequency divider circuitry. The wide-range clock signal generation circuitry is configured to generate a wide-range test clock signal for the test circuitry to conduct a structural delay test for on-chip speed grading. The wide-range test clock signal is generated based on a test clock signal associated with the test circuitry, a frequency range selection signal and a frequency setting signal.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

  • MENTOR GRAPHICS CORPORATION

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Cheng, Wu-Tung Lake Oswego, US 92 1213
Huang, Shi-Yu Taoyuan, TW 14 59
Huang, Tzu-Heng Kaohsiung, TW 3 5
Tsai, Kun-Han Lake Oswego, US 17 186

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation

Maintenance Fees

Fee Large entity fee small entity fee micro entity fee due date
7.5 Year Payment $3600.00 $1800.00 $900.00 Dec 11, 2026
11.5 Year Payment $7400.00 $3700.00 $1850.00 Dec 11, 2030
Fee Large entity fee small entity fee micro entity fee
Surcharge - 7.5 year - Late payment within 6 months $160.00 $80.00 $40.00
Surcharge - 11.5 year - Late payment within 6 months $160.00 $80.00 $40.00
Surcharge after expiration - Late payment is unavoidable $700.00 $350.00 $175.00
Surcharge after expiration - Late payment is unintentional $1,640.00 $820.00 $410.00