Memory device including page buffer and method of arranging page buffer having cache latches
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United States of America Patent
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May 8, 2018
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N/A
app pub date -
Jan 4, 2017
filing date -
May 20, 2016
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Abstract
A memory device includes a memory cell array, a plurality of bit lines, and a plurality of page buffers including a plurality of cache latches, exchanging data with the memory cell array through the plurality of bit lines, wherein the plurality of cache latches are arranged in a column direction in parallel with the plurality of bit lines and a row direction perpendicular to the plurality of bit lines, and have a two-dimensional arrangement of M stages in the column direction, where M is a positive integer not corresponding to 2L and L is zero or a natural number.
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