Semiconductor memory apparatus and operating method
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United States of America Patent
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Jun 12, 2018
Issued Date -
Nov 23, 2017
app pub date -
Dec 14, 2016
filing date -
May 18, 2016
priority date (Note) -
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Abstract
A semiconductor memory apparatus, including a first mat which includes a first bit line and a first word line and a second mat which includes a second bit line and a second word line, includes a first bit line driving circuit configured to enable the first bit line in response to a first bit line select signal and a first machine bit line select signal; a second bit line driving circuit configured to enable the second bit line in response to a second bit line select signal and a second machine bit line select signal; a column-related decoding circuit configured to selectively enable the first and second bit line select signals in response to a column address; and a state machine configured to selectively enable the first and second machine bit line select signals in response to the column address.
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