ETHERNET MAGNETICS INTEGRATION
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United States of America Patent
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app pub date -
May 25, 2016
filing date -
May 25, 2016
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Abstract
An integrated circuit is disclosed and includes an Ethernet physical layer (PHY) with a plurality of communication channels. The communication channels coupled to a corresponding plurality of terminals. The integrated circuit further includes a plurality of electrical isolation circuits and a compensation circuit. At least one of the plurality of electrical isolation circuits is coupled to a corresponding one of the plurality of communication channels and electrically isolates the PHY from a corresponding one of the plurality of terminals. The compensation circuit is configured to compensate for at least one of baseline wander and parameter drift associated with at least one of the plurality of isolation circuits. The PHY and the plurality of isolation circuits are integrated on a single substrate.
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