Dynamic random access memory (DRAM) component for high-performance, high-capacity registered memory modules
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United States of America Patent
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Mar 5, 2019
Grant Date -
Dec 7, 2017
app pub date -
Oct 28, 2015
filing date -
Dec 19, 2014
priority date (Note) -
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Abstract
The embodiments described herein describe technologies of dynamic random access memory (DRAM) components for high-performance, high-capacity registered memory modules, such as registered dual in-line memory modules (RDIMMs). One DRAM component may include a set of memory cells and steering logic. The steering logic may include a first data interface and a second data interface. The first and second data interfaces are selectively coupled to a controller component in a first mode and the first data interface is selectively coupled to the controller component in a second mode and the second data interface is selectively coupled to a second DRAM component in the second mode.
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