Top-side connector interface for processor packaging

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United States of America Patent

PATENT NO 10880994
APP PUB NO 20170354031A1
SERIAL NO

15172102

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Abstract

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An apparatus is provided which comprises: a processor die; a processor substrate having a region extended away from the processor die, wherein the processor die is mounted on the processor substrate, wherein the extended region has at least one signal interface which is connectable to a top-side connector; and an interposer coupled to the processor substrate and a motherboard.

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Patent Owner(s)

Patent OwnerAddress
INTEL CORPORATION2200 MISSION COLLEGE BOULEVARD SANTA CLARA CA 95054

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Aoki, Russell S Tacoma, US 52 423
Smalley, Jeffory L East Olympia, US 54 175
Thibado, Jonathan W Beaverton, US 17 51

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