Vertical transistor having uniform bottom spacers

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United States of America Patent

PATENT NO 10032909
SERIAL NO

15422724

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Abstract

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A method of forming a spacer for a vertical transistor is provided. The method includes forming a fin structure that includes a fin on a semiconductor substrate, forming a source junction or a drain junction at an upper surface of the semiconductor substrate and at a base of the fin and epitaxially growing a rare earth oxide (REO) spacer to have a substantially uniform thickness along respective upper surfaces of the source or drain junction and on opposite sides of the fin structure.

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Patent Owner(s)

  • IBM CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Cheng, Kangguo Schenectady, US 3073 29638
Li, Juntao Cohoes, US 578 3109
Wang, Geng Stormville, US 211 2416
Zhang, Qintao Mt Kisco, US 81 511

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