CUSTOMER-TRANSPARENT LOGIC REDUNDANCY FOR IMPROVED YIELD

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United States of America Patent

SERIAL NO

15700597

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Abstract

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Systems and methods are provided for implementing customer-transparent logic redundancy in scan chains for improved yield of integrated circuits. More specifically, an integrated circuit structure is provided for that includes a plurality of combined latch structures. Each of the combined latch structures includes an original latch and a redundant latch. The integrated circuit structure further includes a plurality of combined logic structures. Each of the combined logic structures includes an original logic structure a redundant logic structure. Each redundant latch is a duplicate of each respective original latch within a combined latch structure and each redundant logic structure is a duplicate of each respective original logic structure within a combined logic structure such that a two-fold library of latches and logic is provided for one or more scan chains of the integrated circuit structure.

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Patent Owner(s)

Patent OwnerAddress
INTERNATIONAL BUSINESS MACHINES CORPORATIONNEW ORCHARD ROAD ARMONK NY 10504

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
ARSOVSKI, Igor Williston, US 117 1327
GOSS, John R South Burlington, US 25 119
HUNT-SCHROEDER, Eric D South Burlington, US 34 89
KILLORIN, Andrew K Weybridge, US 5 12

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