Arithmetic processing unit and control method for arithmetic processing unit
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United States of America Patent
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May 28, 2019
Grant Date -
Dec 28, 2017
app pub date -
Jun 7, 2017
filing date -
Jun 22, 2016
priority date (Note) -
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status (Latency Note)
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Abstract
An apparatus includes: a cache to retain an instruction; an instruction-control circuit to read out the instruction from the cache; and an instruction-execution circuit to execute the instruction read out from the cache, wherein the cache includes: a pipeline processing circuit including a plurality of selection stages in each of which, among a plurality of requests for causing the cache to operate, a request having a priority level higher than priority levels of other requests is outputted to a next stage and a plurality of processing stages in each of which processing based on a request outputted from a last stage among the plurality of selection stages is sequentially executed; and a cache-control circuit to input a request received from the instruction-control circuit to the selection stage in which processing order of the processing stage is reception order of the request.
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