Migrating operating system interference events to a second set of logical processors along with a set of timers that are synchronized using a global clock

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United States of America Patent

PATENT NO 10733032
APP PUB NO 20170371725A1
SERIAL NO

15685506

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Abstract

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A method, information processing system, and computer program product are provided for managing operating system interference on applications in a parallel processing system. A mapping of hardware multi-threading threads to at least one processing core is determined, and first and second sets of logical processors of the at least one processing core are determined. The first set includes at least one of the logical processors of the at least one processing core, and the second set includes at least one of a remainder of the logical processors of the at least one processing core. A processor schedules application tasks only on the logical processors of the first set of logical processors of the at least one processing core. Operating system interference events are scheduled only on the logical processors of the second set of logical processors of the at least one processing core.

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Patent Owner(s)

  • INTERNATIONAL BUSINESS MACHINE CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Divirgilio, John Washingtonville, US 8 163
Fong, Liana L Irvington, US 36 552
Lewars, John New Paltz, US 17 61
Seelam, Seetharami R Yorktown Heights, US 44 533
Veale, Brian F Cedar Park, US 7 55

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