Parity for instruction packets
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United States of America Patent
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Oct 23, 2018
Grant Date -
Dec 28, 2017
app pub date -
Jun 24, 2016
filing date -
Jun 24, 2016
priority date (Note) -
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status (Latency Note)
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Abstract
Systems and method of error checking for instructions method of error checking for instructions include an assembler for creating an instruction packet with one or more instructions, determining if a parity of the instruction packet matches a predesignated parity, and if the parity of the instruction packet does not match the predesignated parity, using a bit of the instruction packet to change parity of the instruction packet to match the predesignated parity. The instruction packet with the predesignated parity is stored in a memory, and may eventually be retrieved by a processor for execution. If there is an error in the instruction packet retrieved from the memory, the error is detected based on comparing the parity of the instruction packet to the predesignated parity.
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