Non-volatile storage system using two pass programming with bit error control
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United States of America Patent
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Apr 2, 2019
Grant Date -
Dec 28, 2017
app pub date -
Jun 24, 2016
filing date -
Jun 24, 2016
priority date (Note) -
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Abstract
A first phase of a programming process is performed to program data into a set of non-volatile memory cells using a set of verify references and allowing for a first number of programming errors. After completing the first phase of programming, an acknowledgement is provided to the host that the programming was successful. The memory system reads the data from the set of non-volatile memory cells and uses an error correction process to identify and correct error bits in the data read. When the memory system is idle and after the acknowledgement is provided to the host, the memory system performs a second phase of the programming process to program the corrected error bits into the set of the non-volatile memory cells using the same set of verify references and allowing for a second number of programming errors.
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