SELF-AWARE, PEER-TO-PEER CACHE TRANSFERS BETWEEN LOCAL, SHARED CACHE MEMORIES IN A MULTI-PROCESSOR SYSTEM
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Jun 24, 2016
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Jun 24, 2016
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Abstract
Self-aware, peer-to-peer cache transfers between local, shared cache memories in a multi-processor system is disclosed. A shared cache memory system is provided comprising local shared cache memories accessible by an associated central processing unit (CPU) and other CPUs in a peer-to-peer manner. When a CPU desires to request a cache transfer (e.g., in response to a cache eviction), the CPU acting as a master CPU issues a cache transfer request. In response, target CPUs issue snoop responses indicating their willingness to accept the cache transfer. The target CPUs also use the snoop responses to be self-aware of the willingness of other target CPUs to accept the cache transfer. The target CPUs willing to accept the cache transfer use a predefined target CPU selection scheme to determine its acceptance of the cache transfer. This can avoid a CPU making multiple requests to find a target CPU for a cache transfer.
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Patent Owner(s)
Patent Owner | Address | |
---|---|---|
QUALCOMM INCORPORATED | 5775 MOREHOUSE DRIVE SAN DIEGO CA 92121-1714 |
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Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Bell,, JR Robert | Raleigh, US | 2 | 4 |
Herold, Brad | Austin, US | 1 | 3 |
Le, Hien Minh | Cedar Park, US | 23 | 369 |
Robinson, Eric Francis | Raleigh, US | 18 | 65 |
Truong, Thuong Quang | Austin, US | 38 | 351 |
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