Sharing global route topologies in detailed routing
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United States of America Patent
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Dec 4, 2018
Grant Date -
Dec 28, 2017
app pub date -
Feb 22, 2017
filing date -
Jun 24, 2016
priority date (Note) -
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status (Latency Note)
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Abstract
According to an aspect, a method includes accessing an initial layout of global wires and a congestion related metric for each net in a gate level design description of an integrated circuit. A second layout is accessed that specifies, for each net, detailed routing information that includes connections between specific wires in the regions of the integrated circuit. A list of nets with a same source region and target region in the initial layout as the failing net is generated. A net in the list of nets is selected and the failing net is rerouted over the selected net. The rerouting includes the global router updating the initial layout and the detailed router updating the second layout. The congestion related metric for each net is updated in response to the global router updating the initial layout.
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