Fin pitch scaling for high voltage devices and low voltage devices on the same wafer
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United States of America Patent
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Apr 23, 2019
Grant Date -
Dec 28, 2017
app pub date -
Aug 18, 2017
filing date -
Nov 23, 2015
priority date (Note) -
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Abstract
A semiconductor device is provided that includes a first plurality of fin structures having a first width in a first region of a substrate, and a second plurality of fin structures having a second width in a second region of the substrate, the second width being less than the first width. A first gate structure is formed on the first plurality of fin structures including a first high-k gate dielectric that is in direct contact with a channel region of the first plurality of fin structures and a first gate conductor. A second gate structure is formed on the second plurality of fin structures including a high voltage gate dielectric that is in direct contact with a channel region of the second plurality of fin structures, a second high-k gate dielectric and a second gate conductor.
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